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19-1173; Rev 2; 5/98
KIT ATION EVALU ABLE AVAIL
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface
General Description Features
o 8-Channel Single-Ended or 4-Channel Differential Inputs o Operates from Single +5V or Dual 5V Supplies o User-Adjustable Output Logic Levels (2.7V to 5.25V) o Low Power: 1.5mA (operating mode) 2A (power-down mode) o Internal Track/Hold, 133kHz Sampling Rate o Internal 4.096V Reference (MAX1202) o SPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar/Bipolar Inputs o 20-Pin DIP/SSOP
MAX1202/MAX1203
The MAX1202/MAX1203 are 12-bit data-acquisition systems specifically designed for use in applications with mixed +5V (analog) and +3V (digital) supply voltages. They operate with a single +5V analog supply or dual 5V analog supplies, and combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. A 4-wire serial interface connects directly to SPITM/MICROWIRETM devices without external logic, and a serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1202/MAX1203 use either the internal clock or an external serial-interface clock to perform successiveapproximation analog-to-digital conversions. The serial interface operates at up to 2MHz. The MAX1202 features an internal 4.096V reference, while the MAX1203 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim. They also have a VL pin that is the power supply for the digital outputs. Output logic levels (3V, 3.3V, or 5V) are determined by the value of the voltage applied to this pin. These devices provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices. A quick turn-on time enables the MAX1202/MAX1203 to be shut down between conversions, allowing the user to optimize supply currents. By customizing powerdown between conversions, supply current can drop below 10A at reduced sampling rates. The MAX1202/MAX1203 are available in 20-pin SSOP and DIP packages, and are specified for the commercial, extended, and military temperature ranges.
Ordering Information
PART MAX1202ACPP MAX1202BCPP MAX1202ACAP MAX1202BCAP MAX1202BC/D TEMP. RANGE PIN-PACKAGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP Dice* INL (LSB) 1/2 1 1/2 1 1
Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only.
Pin Configuration
TOP VIEW
CH0 1 2 3 4 5 6 7 8 9 20 VDD 19 SCLK 18 CS
Applications
5V/3V Mixed-Supply Systems Data Acquisition High-Accuracy Process Control Battery-Powered Instruments Medical Instruments
Typical Operating Circuit appears at end of data sheet. SPI is a registered trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp.
CH1 CH2 CH3 CH4 CH5 CH6 CH7 VSS
MAX1202 MAX1203
17 DIN 16 SSTRB 15 DOUT 14 VL 13 GND 12 REFADJ 11 REF
SHDN 10
DIP/SSOP
________________________________________________________________ Maxim Integrated Products
1
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................-0.3V to 6V VL ...............................................................-0.3V to (VDD + 0.3V) VSS to GND .................................................................0.3V to -6V VDD to VSS ................................................................-0.3V to 12V CH0-CH7 to GND ............................(VSS - 0.3V) to (VDD + 0.3V) CH0-CH7 Total Input Current...........................................20mA REF to GND ................................................-0.3V to (VDD + 0.3V) REFADJ to GND .........................................-0.3V to (VDD + 0.3V) Digital Inputs to GND .................................-0.3V to (VDD + 0.3V) Digital Outputs to GND .................................-0.3V to (VL + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 11.11mW/C above +70C) ...........889mW SSOP (derate 8.00mW/C above +70C) .....................640mW CERDIP (derate 11.11mWC above +70C) .................889mW Operating Temperature Ranges MAX1202_C_P/MAX1203_C_P ............................0C to +70C MAX1202_E_P/MAX1203_E_P..........................-40C to +85C MAX1202BMJP/MAX1203BMJP .....................-55C to +125C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%, VL = 2.7V to 3.6V; VSS = 0V or -5V 5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error MAX1202 (all grades) Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise + Distortion Ratio Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD THD SFDR VIN = 4.096Vp-p, 65kHz (Note 4) -3dB rolloff 80 -85 4.5 800 70 -80 External reference, 4.096V External reference, 4.096V MAX1203A MAX1203B 0.8 0.1 INL DNL MAX1202A/MAX1203A MAX1202B/MAX1203B No missing codes over temperature 12 0.5 1.0 1.0 3.0 3 1.5 3 ppm/C LSB LSB Bits LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar-input mode) dB dB dB dB MHz kHz
2
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, VL = 2.7V to 3.6V; VSS = 0V or -5V 5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External compensation mode, 4.7F External Clock Frequency Range ANALOG INPUT Input Voltage Range, SingleEnded and Differential (Note 7) Multiplexer Leakage Current Input Capacitance REF Output Voltage REF Short-Circuit Current MAX1202AC VREF Temperature Coefficient Load Regulation (Note 8) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Adjustment Range EXTERNAL REFERENCE AT REF (Reference buffer disabled, VREF = 4.096V) Input Voltage Range Input Current Input Resistance REF Input Current in Shutdown REFADJ Buffer Disable Threshold SHDN = 0V VDD 50mV 12 2.50 200 20 1.5 10 VDD + 50mV 350 V A k A V MAX1202AE MAX1202B 0mA to 0.5mA output load Internal compensation mode External compensation mode 0 4.7 0.01 1.5 30 30 30 2.5 mV F F % Unipolar, VSS = 0V Bipolar, VSS = -5V On/off leakage current, VCH_ = 5V (Note 6) TA = +25C 4.076 0.01 16 4.096 4.116 30 50 60 ppm/C VREF VREF / 2 1 V A pF V mA Internal compensation mode (Note 6) Used for data transfer only 0.1 0.1 0 tCONV tACQ Internal clock External clock, 2MHz, 12 clocks/conversion 5.5 6 1.5 10 <50 1.7 2.0 0.4 2.0 MHz 10 s s ns ps MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, VL = 2.7V to 3.6V; VSS = 0V or -5V 5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Internal compensation mode External compensation mode MAX1202 MAX1203 MAX1202 MAX1203 VDD VSS Operating mode Positive Supply Current IDD Fast power-down (Note 9) Full power-down (Note 9) Negative Supply Current Logic Supply Voltage Logic Supply Current (Notes 6, 10) Positive Supply Rejection (Note 11) Negative Supply Rejection (Note 11) Logic Supply Rejection (Note 12) ISS VL IVL PSR PSR PSR VL = VDD = 5V VDD = 5V 5%; external reference, 4.096V; full-scale input VSS = -5V 5%; external reference, 4.096V; full-scale input External reference, 4.096V; full-scale input 0.06 0.01 0.06 Operating mode and fast power-down Full power-down 2.70 5 5% 0 or -5 5% 1.5 30 2 2.5 70 10 50 10 5.25 10 0.5 0.5 0.5 MIN 0 4.7 1.68 1.64 50 5 TYP MAX UNITS EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at REF Reference-Buffer Gain REFADJ Input Current POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage F V/V A A V V mA A A A V A mV mV mV
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, VL = 2.7V to 3.6V; VSS = 0V or -5V 5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Mid-Voltage SHDN Voltage, Floating SHDN Input Low Voltage SHDN Input Current, High SHDN Input Current, Low SHDN Maximum Allowed Leakage, Mid-Input SYMBOL VIH VIL VHYST IIN CIN VSH VSM VFLT VSL ISH ISL SHDN = VDD SHDN = 0V SHDN = open -4.0 -100 100 SHDN = open VIN = 0V or VDD (Note 6) VDD - 0.5 1.5 2.75 0.5 4.0 VDD - 1.5 0.15 1 15 CONDITIONS MIN 2.0 0.8 TYP MAX UNITS V V V A pF V V V V A A nA DIGITAL INPUTS: DIN, SCLK, CS, SHDN
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 2.7V to 3.6V) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT ISINK = 3mA ISINK = 6mA ISOURCE = 1mA CS = VL CS = VL (Note 6) ISINK = 5mA ISINK = 8mA ISOURCE = 1mA CS = 5V CS = 5V (Note 6) 4 10 15 0.3 VL - 0.5 10 15 0.4 0.3 0.4 V V A pF
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 4.75V to 5.25V) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT V V A pF
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
TIMING CHARACTERISTICS
(VDD = +5V 5%, VL = 2.7V to 3.6V, VSS = 0V or -5V 5%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable (Note 6) CS Rise to SSTRB Output Disable (Note 6) SSTRB Rise to SCLK Rise (Note 6) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK CLOAD = 100pF External-clock mode only, CLOAD = 100pF External-clock mode only, CLOAD = 100pF Internal-clock mode only 0 CLOAD = 100pF CLOAD = 100pF CLOAD = 100pF 100 0 200 200 240 240 240 20 CONDITIONS MIN 1.5 100 0 240 240 240 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns ns ns ns ns
Tested at VDD = 5.0V; VSS = 0V; unipolar-input mode. Relative accuracy is the analog value's deviation (at any code) from its theoretical value after the full-scale range is calibrated. MAX1202--internal reference, offset nulled; MAX1203--external reference (VREF = 4.096V), offset nulled. On-channel grounded; sine wave applied to all off-channels. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Guaranteed by design. Not subject to production testing. Common-mode range for analog inputs is from VSS to VDD. External load should not change during the conversion for specified accuracy. Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND; REFADJ = GND. Shutdown supply current is also dependent on VIH (Figure 12c). Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB. Note 11: Measured at VSUPPLY + 5% and VSUPPLY - 5% only. Note 12: Measured at VL = 2.7V and VL = 3.6V.
6
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface
__________________________________________Typical Operating Characteristics
(VDD = 5V 5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = +25C; unless otherwise noted.) SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT SUPPLY CURRENT vs. TEMPERATURE vs. TEMPERATURE vs. SUPPLY VOLTAGE
MAX1202 TOC02
MAX1202 TOC01
MAX1202/MAX1203
SHUTDOWN SUPPLY CURRENT (A)
1.8 SUPPLY CURRENT (mA)
2.5 SUPPLY CURRENT (mA) 2.0 MAX1202 1.5 1.0 0.5 0 MAX1203
5 4 3 2 1 0
REFADJ = GND FULL POWER-DOWN
1.6 MAX1202 1.4
1.2 MAX1203 1.0 4.5 4.7 4.9 5.1 5.3 5.5 SUPPLY VOLTAGE (V)
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (C)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX1202 TOC04
OFFSET ERROR vs. TEMPERATURE
MAX1202 TOC05
GAIN ERROR vs. TEMPERATURE
4 3 GAIN ERROR (LSB) 2 1 0 -1 -2 DIFFERENTIAL SINGLE-ENDED
MAX1202 TOC06
0.8 0.7 0.6 INL (LSB) 0.5 0.4 0.3 0.2 0.1 0 -60 -20 20 60 100
2.0 1.5 OFFSET ERROR (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
5
-3 -4 -5 -60 -20 20 60 100 140 -60 -20 20 60 100 140 TEMPERATURE (C) TEMPERATURE (C)
140
TEMPERATURE (C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX1202 TOC07
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE
4 GAIN-ERROR MATCHING (LSB) 3 2 1 0 -1 -2 -3 -4
MAX1202 TOC08
3 OFFSET-ERROR MATCHING (LSB) 2 1 0 -1 -2 -3 -60 -20 20 60 100
5
-5 140 -60 -20 20 60 100 140 TEMPERATURE (C) TEMPERATURE (C)
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MAX1202 TOC03
2.0
3.0
6
7
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
____________________________Typical Operating Characteristics (continued)
(VDD = 5V 5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202--4.7F capacitor at REF pin; MAX1203--external reference, VREF = 4.096V applied to REF pin; TA = +25C; unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL FFT PLOT
MAX1202 TOC09
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 750 1500 2250 3000 3750
VSS = -5V 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120
4500
0
33.25 FREQUENCY (kHz)
66.50
DIGITAL CODE
______________________________________________________________Pin Description
PIN 1-8 9 NAME CH0-CH7 VSS SHDN Sampling Analog Inputs Negative Supply Voltage. Tie VSS to -5V 5% or to GND. Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10A (max) supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to VDD puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the referencebuffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier. Ground; IN- Input for Single-Ended Conversions Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of the Digital Outputs (DOUT, SSTRB). 2.7V VL 5.25V. Serial-Data Output. Data is clocked out at SCLK's falling edge. High impedance when CS is high. Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin the analog-to-digital conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). Serial-Data Input. Data is clocked in at SCLK's rising edge. Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.) Positive Supply Voltage, +5V 5% FUNCTION
10
11 12 13 14 15 16 17 18 19 20
REF REFADJ GND VL DOUT SSTRB DIN CS SCLK VDD
8
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MAX1202 TOC10
1.0
20
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
+3.3V
DOUT
DOUT
3k
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 GND
18 19 17 10 1 2 3 4 5 6 7 8 13
3k GND a. High-Z to VOH and VOL to VOH
CLOAD
CLOAD GND b. High-Z to VOL and VOH to VOL
INPUT SHIFT REGISTER
INT CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER
15 16
DOUT SSTRB
Figure 1. Load Circuits for Enable Time
+3.3V
ANALOG INPUT MUX
T/H CLOCK IN 12-BIT SAR ADC OUT REF A 1.68
3k DOUT DOUT
MAX1202 MAX1203
+2.44V REFERENCE (MAX1202) 20k
20 14 9
VDD VL VSS
3k GND a. VOH to High-Z
CLOAD
CLOAD GND b. VOL to High-Z
REFADJ REF
12 11
+4.096V
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
_______________Detailed Description
The MAX1202/MAX1203 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to 3V microprocessors (Ps). Figure 3 is the MAX1202/MAX1203 block diagram.
Pseudo-Differential Input
Figure 4 shows the ADC's analog comparator's sampling architecture. In single-ended mode, IN+ is internally switched to CH0-CH7 and IN- is switched to GND. In differential mode, IN+ and IN- are selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels using Tables 3 and 4. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential such that only the signal at IN+ is sampled. The return side (IN-) must remain stable (typically within 0.5LSB, within 0.1LSB for best results)
with respect to GND during a conversion. To do this, connect a 0.1F capacitor from IN- (of the selected analog input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the input control word's last bit is entered. The T/H switch opens at the end of the acquisition interval, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply GND. This unbalances node ZERO at the comparator's input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V IN +) - (V IN -)] from C HOLD to the binaryweighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
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5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
Track/Hold
The T/H enters tracking mode on the falling clock edge after the fifth bit of the 8-bit control word is shifted in. The T/H enters hold mode on the falling clock edge after the eighth bit of the control word is shifted in. IN- is connected to GND if the converter is set up for single-ended inputs, and the converter samples the "+" input. IN- connects to the "-" input if the converter is set up for differential inputs, and the difference of |N+ - IN- is sampled. The positive input connects back to IN+, at the end of the conversion, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, acquisition time increases and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by the following: tACQ = 9 x (RS + RIN) x 16pF where RIN = 9k, RS = the source impedance of the input signal, and tACQ is never less than 1.5s. Source impedances below 1k do not significantly affect the ADC's AC performance. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's signal bandwidth.
12-BIT CAPACITIVE DAC REF
INPUT MUX
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 GND
-
CHOLD + 16pF
COMPARATOR ZERO
CSWITCH TRACK
9k RIN HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
T/H SWITCH
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = GND. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
Figure 4. Equivalent Input Circuit
+3V 0.1F
VL
VDD 0.1F GND VSS 4.7F
+5V
OSCILLOSCOPE
SCLK
0V TO 4.096V ANALOG 0.01F INPUT
CH7
MAX1202 MAX1203
SSTRB CS SCLK DIN SSTRB +3V 2MHz OSCILLATOR CH1 CH2 CH3 CH4 DOUT*
REFADJ REF C2 0.01F C1 4.7F +2.5V +2.5V REFERENCE **
DOUT SHDN N.C.
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX). **REQUIRED FOR MAX1203 ONLY.
Figure 5. Quick-Look Circuit
10 ______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
Table 1a. Unipolar Full Scale and Zero Scale
REFERENCE Internal External at REFADJ at REF ZERO SCALE 0V 0V 0V FULL SCALE +4.096V VREFADJ x A* VREF External
Table 1b. Bipolar Full Scale, Zero Scale, and Negative Full Scale
REFERENCE Internal at REFADJ at REF NEGATIVE ZERO FULL SCALE FULL SCALE SCALE -4.096V / 2 -1/2 VREFADJ x A* -1/2 VREF 0V 0V 0V +4.096V / 2 +1/2 VREFADJ x A* +1/2 VREF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
Input Bandwidth
The ADC's input tracking circuitry has a 4.5MHz small-signal bandwidth. Therefore it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result shifts out of DOUT. Varying the analog input to CH7 alters the sequence of bits from DOUT. A total of 15 clock cycles per conversion is required. All SSTRB and DOUT output transitions occur on SCLK's falling edge.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog inputs to VDD and VSS, allow the analog input pins to swing from (VSS - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV, or be lower than VSS by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off-channels more than 2mA. The full-scale input voltage depends on the voltage at REF (Tables 1a and 1b).
How to Start a Conversion
Clocking a control byte into DIN starts conversion on the MAX1202/MAX1203. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1202/ MAX1203's internal shift register. After CS falls, the first logic "1" bit defines the control byte's MSB. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 2 shows the control-byte format. The MAX1202/MAX1203 are fully compatible with SPI/MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE and SPI both transmit and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the MAX1202/MAX1203's analog performance. The MAX1202/MAX1203 require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds in control byte $FF hex, which triggers single-ended unipolar conversions on CH7 in external clock mode
______________________________________________________________________________________
11
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
Table 2. Control-Byte Format
Bit 7 (MSB) START Bit 7 (MSB) 6 5 4 3 Bit 6 SEL 2 Name START SEL2 SEL1 SEL0 UNI/BIP Bit 5 SEL 1 Bit 4 SEL 0 Bit 3 UNI/BIP Bit 2 SGL/DIF Bit 1 PD1 Bit 0 (LSB) PD0
Description The first logic 1 bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels is used for the conversion (Tables 3 and 4). 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF / 2 to +VREF / 2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to GND. In differential mode, the voltage difference between two channels is measured. (Tables 3 and 4.) Selects clock and power-down modes. PD1 PD0 Mode 0 0 Full power-down (IDD = 2A, internal reference) 0 1 Fast power-down (IDD = 30A, internal reference) 1 0 Internal clock mode 1 1 External clock mode
2
SGL/DIF
1 0 (LSB)
PD1 PD0
D Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4 CH5 CH6 CH7 GND - - - - - - - -
D Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 - + - + - + - + CH0 + CH1 - + - + - + - CH2 CH3 CH4 CH5 CH6 CH7
12
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface
Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and call it TB1. TB1's format should be: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS on the MAX1202/MAX1203 low. 3) Transmit TB1 and simultaneously receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and simultaneously receive byte RB3. 6) Pull CS on the MAX1202/MAX1203 high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure that the total conversion time does not exceed 120s.
Digital Output In unipolar-input mode, the output is straight binary (Figure 15); for bipolar inputs, the output is two'scomplement (Figure 16). Data is clocked out at SCLK's falling edge in MSB-first format. The digital output logic level is adjusted with the VL pin. This allows DOUT and SSTRB to interface with 3V logic without the risk of overdrive. The MAX1202/MAX1203's digital inputs are designed to be compatible with 5V CMOS logic as well as 3V logic.
MAX1202/MAX1203
Internal and External Clock Modes
The MAX1202/MAX1203 can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1202/ MAX1203. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7-10 show the timing characteristics common to both modes.
External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the A/D conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 8 shows SSTRB timing in external clock mode.
CS tACQ SCLK
1 4 UNI/ BIP SGL/ DIF PD1 8 12 16 20 24
DIN
START
SEL2 SEL1 SEL0
PD0
SSTRB RB1 DOUT ACQUISITION 1.5s (SCLK = 2MHz)
B11 MSB B10 B9
RB2
B8 B7 B6 B5 B4 B3 B2 B1
RB3
B0 LSB
FILLED WITH ZEROS IDLE
ADC STATE
IDLE
CONVERSION
Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)
______________________________________________________________________________________ 13
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
CS ***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 7. Detailed Serial-Interface Timing
CS tSDV SSTRB
***
*** tSTR
***
***
tSSTRB
tSSTRB
SCLK
***
***
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
The conversion must complete in some minimum time or droop on the sample-and-hold capacitors might degrade conversion results. Use internal clock mode if the clock period exceeds 10s or if serial-clock interruptions could cause the conversion interval to exceed 120s.
Internal Clock In internal clock mode, the MAX1202/MAX1203 generate their own conversion clock. This frees the P from running the SAR conversion clock, and allows the conversion results to be read back at the processor's
convenience, at any clock rate from zero to 2MHz. SSTRB goes low at the start of the conversion, then goes high when the conversion is complete. SSTRB is low for a maximum of 10s, during which time SCLK should remain low for best noise performance. An internal register stores data while the conversion is in progress. SCLK clocks the data out at this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does not need to be held low once a
14
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
CS
SCLK
1
2
3
4
5 UNI/ BIP
6
7
8
9
10
11
12
18
19
20
21
22
23
24
DIN
START
SEL2 SEL1 SEL0
SGL/ DIF PD1
PD0
SSTRB tCONV DOUT ACQUISITION 1.5s (SCLK = 2MHz) CONVERSION 10s MAX
B11 MSB B10 B9 B2 B1 B0 LSB
FILLED WITH ZEROS
ADC STATE
IDLE
IDLE
Figure 9. Internal Clock Mode Timing
CS * * *
tCONV tCSH SSTRB * * * tSSTRB SCLK * * * tSCK
tCSS
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
conversion is started. Pulling CS high prevents data from being clocked into the MAX1202/MAX1203 and threestates DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 10 shows SSTRB timing in internal clock mode. Data can be shifted in and out of the MAX1202/MAX1203 at clock rates up to 2.0MHz, if tACQ is kept above 1.5s.
after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as one of the following: The first high bit clocked into DIN with CS low anytime the converter is idle (e.g., after VDD is applied). or The first high bit clocked into DIN after bit 5 (B5) of a conversion in progress appears at DOUT. If a falling edge on CS forces a start bit before B5 becomes available, the current conversion is terminated and a new one started. Thus, the fastest the MAX1202/MAX1203 can run is 15 clocks/conversion.
15
Data Framing
CS's falling edge does not start a conversion on the MAX1202/MAX1203. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK's falling edge
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers (Cs) require that data transfers occur in multiples of eight clock cycles; 16 clocks per conversion is typically the fastest that a C can drive the MAX1202/MAX1203. Figure 11b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. For the MAX1202, fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30A. Power-up time can be shortened to 5s in internal compensation mode. Since the MAX1203 does not have an internal reference, power-up times coming out of full or fast power-down are identical. IDD shutdown current can increase if any digital input (DIN, SCLK, CS) is held high in either power-down mode. The actual shutdown current depends on the state of the digital inputs, the voltage applied to the digital inputs (VIH), the supply voltage (VDD), and the operating temperature. Figure 12c shows the maximum IDD increase for each digital input held high in power-down mode for different operating conditions. This current is cumulative, so if all three digital inputs are held high, the additional shutdown current is three times the value shown in Figure 12c. In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Table 5 shows how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7F compensation capacitor (200ms with a 33F capacitor) when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2LSB while shut down. In power-down, the capacitor has to supply the current into the reference (typically 1.5A) and the transient currents at power-up. Figures 12a and 12b show the various power-down sequences in both external and internal clock modes.
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1202/MAX1203 in internal clock mode, ready to convert with SSTRB = high. After the power supplies are stabilized, the internal reset time is 100s. No conversions should be performed during this phase. SSTRB is high on power-up, and if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN also selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. Compensated or not, the minimum clock rate is 100kHz due to droop on the sample-and-hold. Float SHDN to select external compensation. The Typical Operating Circuit uses a 4.7F capacitor at REF. A value of 4.7F or greater ensures stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see the section Choosing Power-Down Mode, and Table 5). Internal compensation requires no external capacitor at REF, and is selected by pulling SHDN high. Internal compensation allows for the shortest power-up times, but the external clock must be limited to 400kHz during the conversion.
Power-Down
Choosing Power-Down Mode You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or floating (Tables 2 and 6). Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. Full power-down mode turns off all chip functions that draw quiescent current, reducing IDD and ISS typically to 2A.
16
Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 6, PD1 and PD0 also specify the clock mode. When software power-down is asserted, the ADC continues to operate in the last specified clock mode until the conversion is complete. The ADC then powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results can be clocked out even though the MAX1202/MAX1203 have already entered software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX1202/MAX1203. Following the start bit, the control byte also determines clock and power-down modes. For example, if the DIN word contains PD1 = 1, the chip remains powered up. If PD1 = 0, power-down resumes after one conversion.
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
CS 1 SCLK DIN DOUT SSTRB S CONTROL BYTE 0
B11 B10 B9 B8
8
1
8
1
S
B7 B6 B5 B4 B3
CONTROL BYTE 1
B2 B1 B0 B11 B10 B9 B8 B7 B6
S
CONTROL BYTE 2
B1 B0
B5 B4 B3 B2
CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS SCLK DIN DOUT S CONTROL BYTE 0 S CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5
*** *** *** ***
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Hardware Power-Down The SHDN pin places the converter into full power-down mode. Unlike the software power-down modes, conversion is not completed; it stops coincidentally with SHDN being brought low. There is no power-up delay if an external reference, which is not shut down, is used. SHDN also selects internal or external reference compensation (Table 7).
bypass capacitor at REFADJ forms an RC filter with the internal 20k reference resistor, with a 0.2ms time constant. To achieve full 12-bit accuracy, 10 time constants (or 2ms in this example) are required for the reference buffer to settle. When exiting FULLPD, waiting this 2ms in FASTPD mode (instead of just exiting FULLPD mode and returning to normal operating mode) reduces power consumption by a factor of 10 or more (Figure 13).
Power-Down Sequencing
The MAX1202/MAX1203's automatic power-down modes can save considerable power when operating at less than maximum sample rates. The following sections discuss the various power-down sequences.
Lowest Power at up to 500 Conversions per Channel per Second Figure 14a depicts MAX1202 power consumption for one or eight channel conversions using full power-down mode and internal reference compensation. A 0.01F
Lowest Power at Higher Throughputs Figure 14b shows power consumption with externalreference compensation in fast power-down, with one and eight channels converted. The external 4.7F compensation requires a 50s wait after power-up. This circuit combines fast multichannel conversion with the lowest power consumption possible. Full power-down mode can increase power savings in applications where the MAX1202/MAX1203 are inactive for long periods of time, but where intermittent bursts of high-speed conversion are required.
17
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN
SXXXXX11 SXXXXX01
INTERNAL
EXTERNAL
EXTERNAL
SETS FAST POWER-DOWN MODE
SETS EXTERNAL CLOCK MODE
SXX XXX1 1
DOUT
DATA VALID (12 DATA BITS)
DATA VALID (12 DATA BITS)
DATA INVALID POWERED UP FAST POWER-DOWN FULL POWERDOWN POWERED UP
MODE
POWERED UP
Figure 12a. Timing Diagram for Power-Down Modes, External Clock
Table 5. Typical Power-Up Delay Times
REFERENCE BUFFER Enabled Enabled Enabled Disabled Disabled REFERENCE-BUFFER COMPENSATION MODE Internal Internal External 4.7 REF CAPACITOR (F) POWER-DOWN MODE Fast Full Fast/Full Fast Full POWER-UP DELAY (s) 5 300 See Figure 14c 2 2 MAXIMUM SAMPLING RATE (ksps) 26 26 133 133 133
Table 6. Software Shutdown and Clock Mode
PD1 0 0 1 1 PD0 0 1 0 1 DEVICE MODE Full power-down mode Fast power-down mode Internal clock mode External clock mode
Table 7. Hard-Wired Shutdown and Compensation Mode
SHDN STATE VDD Floating GND DEVICE MODE Enabled Enabled Full Power-Down REFERENCE-BUFFER COMPENSATION Internal compensation External compensation N/A
18
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
CLOCK MODE INTERNAL CLOCK MODE SETS INTERNAL CLOCK MODE
SXXXXX10 SXXXXX00
SETS FULL POWER-DOWN
S
DIN
DOUT
DATA VALID
DATA VALID
SSTRB MODE
CONVERSION POWERED UP
CONVERSION FULL POWER-DOWN
POWERED UP
Figure 12b. Timing Diagram for Power-Down Modes, Internal Clock
40 SUPPLY CURRENT PER INPUT (A) 35 30 25 20 15 (VDD - VIH) = 2.25V 10 (VDD - VIH) = 1.95V 5 0 -60 -20 20 60 100 140 TEMPERATURE (C) (VDD - VIH) = 2.55V
External and Internal References
The MAX1202 can be used with an internal or external reference, whereas an external reference is required for the MAX1203. An external reference can be connected directly at the REF terminal, or at the REFADJ pin. An internal buffer is designed to provide 4.096V at REF for both the MAX1202 and the MAX1203. The MAX1202's internally trimmed 2.44V reference is buffered with a gain of 1.68. The MAX1203's REFADJ pin is buffered with a gain of 1.64, to scale an external 2.5V reference at REFADJ to 4.096V at REF.
Figure 12c. Additional IDD Shutdown Supply Current vs. VIH for Each Digital Input at a Logic 1
MAX1202 Internal Reference The MAX1202's full-scale range using the internal reference is 4.096V with unipolar inputs and 2.048V with bipolar inputs. The internal reference voltage is adjustable to 1.5% with the circuit of Figure 17.
COMPLETE CONVERSION SEQUENCE 2ms WAIT DIN (ZEROS) 1 FULLPD 2.5V REFADJ 0V 4V REF 0V tBUFFEN 15s = RC = 20k x CREFADJ 00 1 FASTPD 01 1 NOPD CH1 11 1 CH7 00 FULLPD (ZEROS) 1 FASTPD 01
Figure 13. MAX1202 FULLPD/FASTPD Power-Up Sequence
______________________________________________________________________________________ 19
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
FULL POWER-DOWN
2ms FASTPD WAIT 400kHz EXTERNAL CLOCK INTERNAL COMPENSATION 100 8 CHANNELS
MAX186-14A
MAX1202/MAX1203 FAST POWER-DOWN
10,000 AVERAGE SUPPLY CURRENT (A)
1000 AVERAGE SUPPLY CURRENT (A)
8 CHANNELS 1000
1 CHANNEL 10
1 CHANNEL 100 2MHz EXTERNAL CLOCK EXTERNAL COMPENSATION 50s WAIT
1 0 50 100 150 200 250 300 350 400 450 500 CONVERSIONS PER CHANNEL PER SECOND
10 0 2k 4k 6k 8k 10k 12k 14k 16k 18k CONVERSIONS PER CHANNEL PER SECOND
Figure 14a. MAX1202 Supply Current vs. Sample Rate/Second, FULLPD, 400kHz Clock
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample Rate/Second, FASTPD, 2MHz Clock
External Reference With both the MAX1202 and MAX1203, an external reference can be placed at either the input (REFADJ) or the output (REF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20k for the MAX1202, and higher than 100k for the MAX1203, where the internal reference is omitted. At REF, the DC input resistance is a minimum of 12k. During conversion, an external reference at REF must deliver up to 350A DC load current and have an output impedance of 10 or less. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
Using the buffered REFADJ input makes buffering of the external reference unnecessary. When connecting an external reference directly at REF, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ can be as much as 25A with REFADJ tied to VDD (MAX1202 only). Pull REFADJ to GND to minimize the input bias current in power-down.
3.0 2.5 POWER-UP DELAY (ms) 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (sec)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 16 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary with 1LSB = 1.00mV (4.096V/4096) for unipolar operation, and 1LSB = 1.00mV [(4.096V/2 - -4.096V/ 2)/4096] for bipolar operation. Figure 17 shows how to adjust the ADC gain in applications that use the internal reference. The circuit provides 1.5% (65LSBs) of gain adjustment range.
20
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 18 shows the recommended system ground connections. Establish a single-point analog ground
______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
OUTPUT CODE FULL-SCALE TRANSITION 011 . . . 111 011 . . . 110 FS = +2.048V 1LSB = +4.096V 4096 OUTPUT CODE
11 . . . 111 11 . . . 110 11 . . . 101
000 . . . 010 000 . . . 001 FS = +4.096V 1LSB = + 4.096V 4096 000 . . . 000 111 . . . 111 111 . . . 110 00 . . . 011 00 . . . 010 100 . . . 001 00 . . . 001 00 . . . 000 0 1 2 3 FS - 3/2LSB FS -FS 0V INPUT VOLTAGE (LSBs) +FS - 1LSB 100 . . . 000 111 . . . 101
INPUT VOLTAGE (LSBs)
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
Figure 16. Bipolar Transfer Function, 4.096V/2 = Full Scale
("star" ground point) at GND. Connect all other analog grounds to this ground. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the power supplies can affect the ADC's high-speed comparator. Bypass these supplies to the single-point analog ground with 0.1F and 4.7F bypass capacitors close to the MAX1202/MAX1203. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a lowpass filter, as shown in Figure 18.
+5V
MAX1202
510k 100k 12 0.01F REFADJ
24k
Figure 17. MAX1202 Reference-Adjust Circuit
______________________________________________________________________________________
21
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
TMS320CL3x to MAX1202/ MAX1203 Interface
Figure 19 shows an application circuit to interface the MAX1202/MAX1203 to the TMS320 in external clock mode. Figure 20 shows the timing diagram for this interface circuit. Use the following steps to initiate a conversion in the MAX1202/MAX1203 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. The TMS320's CLKX and CLKR are tied together with the MAX1202/MAX1203's SCLK input. 2) The MAX1202/MAX1203's CS is driven low by the TMS320's XF_ I/O port to enable data to be clocked into the MAX1202/MAX1203's DIN. 3) Write an 8-bit word (1XXXXX11) to the MAX1202/ MAX1203 to initiate a conversion and place the device into external clock mode. Refer to Table 2 to select the proper XXXXX bit values for your specific application. 4) The MAX1202/MAX1203's SSTRB output is monitored via the TMS320's FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1202/MAX1203. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1202/MAX1203 until the next conversion is initiated.
SUPPLIES +5V -5V +3V GND
XF CLKX
CS SCLK
TMS320LC3x
R* = 10
CLKR DX DIN DOUT
MAX1202 MAX1203
VDD
GND
VSS
VL
+3V
DGND
DR FSR
MAX1202 MAX1203
*OPTIONAL
DIGITAL CIRCUITRY
SSTRB
Figure 18. Power-Supply Grounding Connection
Figure 19. MAX1202/MAX1203-to-TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0 HIGH IMPEDANCE HIGH IMPEDANCE
SSTRB
DOUT
MSB
B10
B1
LSB
Figure 20. TMS320 Serial-Interface Timing Diagram
22 ______________________________________________________________________________________
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface
_Ordering Information (continued)
PART MAX1202AEPP MAX1202BEPP MAX1202AEAP MAX1202BEAP MAX1202BMJP MAX1203ACPP MAX1203BCPP MAX1203ACAP MAX1203BCAP MAX1203BC/D MAX1203AEPP MAX1203BEPP MAX1203AEAP MAX1203BEAP MAX1203BMJP TEMP. RANGE PIN-PACKAGE -40C to +85C 20 Plastic DIP -40C to +85C -40C to +85C -40C to +85C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP** 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP Dice* 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP** INL (LSB) 1/2 1 1/2 1 1 1/2 1 1/2 1 1 1/2 1 1/2 1 1
0V to 4.096V ANALOG INPUTS CH0 VDD VL
__________Typical Operating Circuit
+5V +3V VDD C3 0.1F GND VSS CS SCLK REF C1 4.7F C2 0.01F REFADJ DIN DOUT SSTRB SHDN VSS I/O SCK (SK) MOSI (SO) MISO (SI) C4 4.7F C5 0.1F
MAX1202/MAX1203
MAX1202
CH7
CPU
*Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability.
___________________Chip Information
TRANSISTOR COUNT: 2503 SUBSTRATE CONNECTED TO VSS
______________________________________________________________________________________
23
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface MAX1202/MAX1203
________________________________________________________Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
PDIPN.EPS

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